S/UNI®-JET Data Sheet
Released
6. IR#3 is the PRGD Pattern Insertion #3 Register
7. IR#4 is the PRGD Pattern Insertion #4 Register
8. The TINV bit and the RINV bit are contained in the PRGD Control Register
13.15 JTAG Support
The S/UNI-JET supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1
standards. The TAP consists of the five standard pins (TRSTB, TCK, TMS, TDI, and TDO) used
to control the TAP controller and the boundary scan registers.
The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test
clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is
used to direct the TAP controller through its states. The basic boundary scan architecture is shown
in Figure 23.
Figure 23 Boundary Scan Architecture
Boundary Scan
TDI
Register
Device Identification
Register
Bypass
Register
Instruction
Mux
Register
DFF
and
TDO
Decode
Control
TMS
Test
Select
Access
Port
Tri-state
Enable
Controller
TRSTB
TCK
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
288
PMC [ PMC-SIERRA, INC ]
