S/UNI®-JET Data Sheet
Released
Figure 20 Typical Data Frame
BIT: 8
7
6
5
4
3
2
1
FLAG
0
1
1
1
1
1
1
0
Address (high)
(low)
data bytes written to the
Transmit Data Register
and serially transmitted,
bit 1 first
CONTROL
Frame Check
Sequence
appended after EOM
is set, if CRC is set
0
1
1
1
1
1
1
0
FLAG
Bit 1 is the first serial bit to be received. When enabled, the primary, secondary and universal
addresses are compared with the high order packet address to determine a match.
Figure 21 shows the timing of interrupts, the state of the FIFO, and the state of the Data Link
relative the input data sequence. The cause of each interrupt and the processing required at each
point is described in the following paragraphs.
Figure 21 Example Multi-Packet Operational Sequence
DATA FF F D D D D F D D D D D D D D DD A FF F F DD D D FF
INT
1
2
3
4 5
6
7
FE
LA
Notes
1. F is the flag sequence (01111110).
2. A is the abort sequence (01111111).
3. D is the packet data bytes.
4. INT is the active high interrupt output.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
284
PMC [ PMC-SIERRA, INC ]
