S/UNI®-JET Data Sheet
Released
The pattern generator consists of a 32-bit shift register and a single XOR gate. The XOR gate
output is fed into the first stage of the shift register. The XOR gate inputs are determined by
values written to the length register (PL[4:0]) and the tap register (PT[4:0], when the PS bit is
low). When PS is high, the pattern detector functions as a recirculating shift register, with length
determined by PL[4:0].
13.14.1 Generating and detecting repetitive patterns
When a repetitive pattern (such as 1-in-8) is to be generated or detected, the PS bit must be set to
logic one. The pattern length register must be set to (N-1), where N is the length of the desired
repetitive pattern. Several examples of programming for common repetitive sequences are given
below in the Common Test Patterns section.
For pattern generation, the desired pattern must be written into the PRGD Pattern Insertion
Registers. The repetitive pattern will then be continuously generated. The generated pattern will
be inserted in the output data stream, but the phase of the pattern cannot be guaranteed.
For pattern detection, the PRGD will determine if a repetitive pattern of the length specified in
the pattern length register exists in the input stream. It does so by loading the first N bits from the
data stream, and then monitoring to see if the pattern loaded repeats itself error free for the
subsequent 48-bit periods. It will repeat this process until it finds a repetitive pattern of length N,
at which point it begins counting errors (and possibly re-synchronizing) in the same way as for
pseudo-random sequences.
Note: The PRGD does not look for the pattern loaded into the Pattern Insertion Registers, but
rather automatically detects any repetitive pattern of the specified length. The precise pattern
detected can be determined by initiating a PRGD update, setting PDR[1:0] = 00 in the PRGD
Control Register, and reading the Pattern Detector Registers, which will then contain the 32 bits
detected immediately prior to the strobe.
13.14.2 Common Test Patterns
The PRGD can be configured to monitor the standardized pseudo random and repetitive patterns
described in ITU-T O.151. The register configurations required to generate these patterns and
others are indicated in the Table 42 and Table 43.
Table 42 Pseudo Random Pattern Generation (PS bit = 0)
Pattern Type
TR
LR
IR#1
IR#2
IR#3
IR#4
TINV
RINV
3
00
02
FF
FF
FF
FF
0
0
2 -1
4
00
01
04
00
03
03
04
05
06
06
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
0
0
0
0
0
0
0
0
0
0
2 -1
5
2 -1
6
2 -1
7
2 -1
7
2 -1 (Fractional T1 LB Activate)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
286
PMC [ PMC-SIERRA, INC ]
