S/UNI®-JET Data Sheet
Released
To initialize the TDPR, the TDPR Configuration Register must be properly set. If FCS generation
is desired, the CRC bit should be set to logic one. If the block is to be used in interrupt driven
mode, then interrupts should be enabled by setting the FULLE, OVRE, UDRE, and LFILLE bits
in the TDPR Interrupt Enable Register to logic one. The TDPR operating parameters in the TDPR
Upper Transmit Threshold and TDPR Lower Interrupt Threshold Registers should be set to the
desired values. The TDPR Upper Transmit Threshold sets the value at which the TDPR
automatically begins the transmission of HDLC packets, even if no complete packets are in the
FIFO. Transmission will continue until current packet is transmitted and the number of bytes in
the TDPR FIFO falls to, or below, this threshold level. The TDPR will always transmit all
complete HDLC packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be
enabled by setting the EN bit to logic one. If no message is sent after the EN bit is set to logic
one, continuous flags will be sent.
The TDPR can be used in a polled or interrupt driven mode for the transfer of data. In the polled
mode the processor controlling the TDPR must periodically read the TDPR Interrupt Status
Register to determine when to write to the TDPR Transmit Data Register. In the interrupt driven
mode, the processor controlling the TDPR uses the INTB output, the S/UNI-JET Clock Activity
Monitor and Interrupt Identification Register, and the S/UNI-JET Interrupt Status Register to
identify TDPR interrupts which determine when writes can or must be done to the TDPR
Transmit Data Register.
13.12.1 Interrupt Driven Mode
The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO.
The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable
Upper Transmit Threshold.
The CRC bit can be set to logic one so that the FCS is generated and inserted at the end of a
packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient
warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic
one so an interrupt on INTB is generated upon detection of a FIFO full state, a FIFO depth below
the lower limit threshold, a FIFO overrun, or a FIFO underrun.
Use the following procedure to transmit HDLC packets:
•
•
•
Wait for data to be transmitted. Once data is available to be transmitted, then go to step 2.
Write the data byte to the TDPR Transmit Data Register.
If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration
Register to logic one. Go to step 1.
•
If there are more bytes in the packet to be sent, then go to step 2.
While performing steps 1 to 3, the processor should monitor for interrupts generated by the
TDPR. When an interrupt is detected, the TDPR Interrupt Routine, described in the following
section, should be immediately followed.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
279
PMC [ PMC-SIERRA, INC ]
