S/UNI®-JET Data Sheet
Released
Register 35CH: TDPR Interrupt Status/UDR Clear
Bit
Type
Function
Unused
FULL
BLFILL
Unused
FULLI
OVRI
UDRI
LFILLI
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
R
R
R
R
R
R
Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR
Transmit Data Register and reads of the TDPR Interrupt Status/UDR Clear Register should not
occur at rates greater than 1/8th that of the clock selected by the LINESYSCLK bit of the S/UNI-
JET Miscellaneous Register (39BH).
LFILLI
The LFILLI bit will transition to logic one when the TDPR FIFO level transitions to empty or
falls below the value of LINT[6:0] programmed in the TDPR Lower Interrupt Threshold
Register. LFILLI will assert INTB if it is a logic one and LFILLE is programmed to logic
one. LFILLI is cleared when this register is read.
UDRI
The UDRI bit will transition to logic one when the TDPR FIFO underruns. That is, the TDPR
is in the process of transmitting a packet when it runs out of data to transmit. UDRI will
assert INTB if it is a logic one and UDRE is programmed to logic one. UDRI is cleared when
this register is read.
OVRI
The OVRI bit will transition to logic one when the TDPR FIFO overruns. That is, the TDPR
FIFO is already full when another data byte is written to the TDPR Transmit Data Register.
OVRI will assert INTB if it is a logic one and OVRE is programmed to logic one. OVRI is
cleared when this register is read.
FULLI
The FULLI bit will transition to logic one when the TDPR FIFO is full. FULLI will assert
INTB if it is a logic one and FULLE is programmed to logic one. FULLI is cleared when this
register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
188
PMC [ PMC-SIERRA, INC ]
