S/UNI®-JET Data Sheet
Released
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Uses the PMC-Sierra™ PM4351 COMET, PM4341 T1XC and PM6341 E1XC T1 and E1
framer/line interface chips for DS1 and E1 applications.
Provides programmable pseudo-random test pattern generation, detection, and analysis
features.
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Provides integral transmit and receive HDLC controller with 128-byte FIFO depth.
Provides performance monitoring counters suitable for accumulation periods of up to 1
second.
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Provides an 8-bit microprocessor interface for configuration, control and status monitoring.
Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
Uses low power 3.3V CMOS technology with 5V tolerant inputs.
Is available in a 256-pin SBGA package (27mm x 27mm).
The receiver section of the S/UNI-JET:
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Provides frame synchronization for the M23 or C-bit parity DS3 applications and alarm
detection. Also:
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Accumulates line code violations, framing errors, parity errors, path parity errors and
FEBE events.
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Detects far end alarm channel codes.
Provides an integral HDLC receiver to terminate the path maintenance data link.
Provides frame synchronization for the G.751 or G.832 E3 applications and alarm detection.
Also:
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Accumulates line code violations, framing errors, parity errors, and FEBE events.
Detects the Trail Trace in G.832, the Trail Trace is detected.
Provides an integral HDLC receiver is provided to terminate either the Network
Requirement or the General Purpose data link.
Provides frame synchronization for G.704 and NTT 6.312 Mbit/s J2 applications and alarm
detection. Also:
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Accumulates line code violations, framing errors, and CRC parity errors.
Provides an integral HDLC receiver to terminate the data link.
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Provides frame synchronization, cell delineation and extraction for DS3, G.751 E3, G.832 E3,
and G.704 and NTT J2 ATM direct-mapped formats.
Provides PLCP frame synchronization, path overhead extraction, and cell extraction for DS1
PLCP, DS3 PLCP, E1 PLCP, and G.751 E3 PLCP formatted streams.
Provides a 50 MHz 8-bit wide or 16-bit wide Utopia FIFO buffer in the receive path with
parity support, and multi-PHY (Level 2) control signals.
Provides ATM framing using cell delineation. Note: ATM cell delineation may optionally be
disabled to allow passing of all cell bytes regardless of cell delineation status.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
18
PMC [ PMC-SIERRA, INC ]
