S/UNI®-JET Data Sheet
Released
List of Tables
Table 1 Supported Operating Formats............................................................................17
Table 2 Transmission System Sublayer Processing Acceptance and Output................29
Table 3 Summary of Receive Detection Features ..........................................................29
Table 4 Multiframe Format ..............................................................................................58
Table 5 C1 Octet Pattern.................................................................................................74
Table 6 Register Memory Map........................................................................................76
Table 7 STATSEL[2:0] Options.......................................................................................86
Table 8 TFRM[1:0] Transmit Frame Structure Configurations........................................88
Table 9 LOF[1:0] Integration Period Configuration .........................................................90
Table 10 RFRM[1:0] Receive Frame Structure Configurations ......................................90
Table 11 SPLR FORM[1:0] Configurations.....................................................................99
Table 12 PLCP LOF Declaration/Removal Times.........................................................104
Table 13 SPLT FORM[1:0] Configurations ...................................................................107
Table 14 DS3 FRMR EXZS/LCV Count Configurations................................................131
Table 15 DS3 FRMR AIS Configurations......................................................................132
Table 16 E3 FRMR FORMAT[1:0] Configurations........................................................141
Table 17 E3 TRAN FORMAT[1:0] Configurations.........................................................154
Table 18 J2 FRMR LOS Threshold Configurations.......................................................161
Table 19 RDLC PBS[2:0] Data Status...........................................................................178
Table 20 RXCP-50 HCS Filtering Configurations .........................................................193
Table 21 RXCP-50 Cell Delineation Algorithm Base ....................................................193
Table 22 RXCP-50 LCD Integration Periods.................................................................201
Table 23 TXCP-50 FIFO Depth Configurations ............................................................213
Table 24 TTB Payload Type Match Configurations ......................................................227
Table 25 PRGD Pattern Detector Register Configuration.............................................237
Table 26 PRGD Generated Bit Error Rate Configurations............................................243
Table 27 Test Mode Register Memory Map..................................................................249
Table 28 Test Mode 0 Input Read Address Locations.................................................251
Table 29 Test Mode 0 Output Write Address Locations ...............................................253
Table 30 Instruction Register ........................................................................................255
Table 31 Identification Register.....................................................................................256
Table 32 Boundary Scan Register ................................................................................256
Table 33 Register Settings for Basic Configurations.....................................................260
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
15
PMC [ PMC-SIERRA, INC ]
