S/UNI®-JET Data Sheet
Released
List of Figures
Figure 1 S/UNI-JET Operating as an ATM PHY in an ATM Switch................................26
Figure 2 S/UNI-JET Operating as a Framer Device in Frame Relay Equipment............27
Figure 3 Block Diagram...................................................................................................28
Figure 4 Framing algorithm (CRC_REFR = 0)................................................................60
Figure 5 Framing Algorithm (CRC_REFR = 1)................................................................61
Figure 6 Cell delineation State Diagram .........................................................................65
Figure 7 HCS Verification State Diagram........................................................................68
Figure 8 DS3 PLCP Frame Format...............................................................................262
Figure 9 DS1 PLCP Frame Format...............................................................................262
Figure 10 G.751 E3 PLCP Frame Format.....................................................................263
Figure 11 E1 PLCP Frame Format................................................................................264
Figure 12 DS3 Frame Structure ....................................................................................267
Figure 13 G.751 E3 Frame Structure............................................................................269
Figure 14 G.832 E3 Frame Structure............................................................................270
Figure 15 J2 Frame Structure .......................................................................................272
Figure 16 16-bit Wide, 26-byte Word Structure.............................................................273
Figure 17 16-bit Wide, 27-byte Word Structure.............................................................274
Figure 18 8-bit Wide, 52-byte Word Structure...............................................................275
Figure 19 8-bit Wide, 53-byte Word Structure...............................................................276
Figure 20 Typical Data Frame.......................................................................................284
Figure 21 Example Multi-Packet Operational Sequence ..............................................284
Figure 22 PRGD Pattern Generator..............................................................................285
Figure 23 Boundary Scan Architecture .........................................................................288
Figure 24 TAP Controller Finite State Machine.............................................................290
Figure 25 Input Observation Cell (IN_CELL) ................................................................293
Figure 26 Output Cell (OUT_CELL) ..............................................................................293
Figure 27 Bi-directional Cell (IO_CELL)........................................................................294
Figure 28 Layout of Output Enable and Bi-directional Cells .........................................294
Figure 29 Receive DS1 Stream.....................................................................................295
Figure 30 Receive E1 Stream .......................................................................................295
Figure 31 Receive Bipolar DS3 Stream ........................................................................296
Figure 32 Receive Unipolar DS3 Stream ......................................................................296
Figure 33 Receive Bipolar E3 Stream...........................................................................296
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
12
PMC [ PMC-SIERRA, INC ]
