S/UNI®-JET Data Sheet
Released
EXZSO
The EXZSO bit enables only summed zero occurrences to be accumulated in the PMON
EXZS Count Registers. When EXZSO is set to logic one, any excessive zeros occurrences
over an 85 bit period increments the PMON EXZS counter by one. When EXZSO is set to
logic zero, summed LCVs are accumulated in the PMON EXZS Count Registers. A summed
LCV is defined as the occurrence of either BPVs not part of a valid B3ZS signature or three
consecutive zeros (or excessive zeros if EXZDET=1) occurring over an 85 bit period; each
summed LCV occurrence increment the PMON EXZS counter by one. Refer to Table 14.
BPVO
The BPVO bit enables only bipolar violations to indicate LCV and be accumulated in the
PMON LCV Count Registers. When BPVO is set to logic one, only BPVs not part of a valid
B3ZS signature generate an LCV indication and increment the PMON LCV counter. When
BPVO is set to logic zero, both BPVs not part of a valid B3ZS signature, and either three
consecutive zeros or excessive zeros generate an LCV indication and increment the PMON
LCV counter. Refer to Table 14.
Table 14 DS3 FRMR EXZS/LCV Count Configurations
Register Bit
Counter Function
PMON EXZ Count
Summed LCVs
EXZSO
BPVO
EXZDET
PMON LCV Count
0
0
0
0
0
1
BPVs & every 3 consecutive zeros
Summed LCVs
BPVs & every string of more than
3 consecutive zeros
0
0
1
1
1
0
0
1
0
Reserved
Reserved
Reserved
Reserved
BPVs & every 3 consecutive zeros
Summed excessive
zeros
1
1
1
0
1
1
1
0
1
Summed excessive
zeros
BPVs & every string of 3+
consecutive zeros
Only BPVs
Summed excessive
zeros
Summed excessive
zeros
Only BPVs
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
131
PMC [ PMC-SIERRA, INC ]
