PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
The T1 framer section:
• Recovers clock and data using a digital phase locked loop for high jitter
tolerance. A direct clock input is provided to allow clock recovery to be
bypassed.
• Accepts dual rail or single rail digital PCM inputs.
• Supports B8ZS or AMI line code.
• Accepts gapped data streams to support higher rate demultiplexing.
• Frames to SF or ESF format DS1 signals. Provides loss of signal detection,
and red, yellow, and AIS alarm detection. Red, yellow, and AIS alarms are
integrated as per industry specifications.
• Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving
192 bit window.
• Provides programmable framed or unframed in-band loopback code
detection.
• Supports line and path performance monitoring according to ANSI
specifications. Accumulators are provided for counting:
• ESF CRC-6 errors to 333 per second;
• Framing bit errors to 31 per second;
• Line code violations to 4095 per second; and
• Loss of frame or change of frame alignment events to 7 per
second.
• Provides ESF bit-oriented code detection, and an HDLC interface for
terminating the ESF data link.
• Supports polled, interrupt-driven, or DMA servicing of the HDLC interface.
• Extracts the data link in ESF mode.
The T1 transmitter section:
• Formats data to SF or ESF format DS1 signals.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
2
PMC [ PMC-SIERRA, INC ]
