PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
FIGURE 22- DIRECT-PHY SELECTION TRANSMIT CELL INTERFACE
(MPHEN = 0) ........................................................................................................
227
FIGURE 23- DIRECT-PHY SELECTION RECEIVE CELL INTERFACE (MPHEN
= 0)
..................................................................................................... 228
FIGURE 24- MULTI-PHY ADDRESSING TRANSMIT CELL INTERFACE
(MPHEN = 1) .................................................................................................. 228
FIGURE 25- MULTI-PHY ADDRESSING RECEIVE CELL INTERFACE (MPHEN
= 1)
..................................................................................................... 229
FIGURE 26- TYPICAL DATA FRAME............................................................. 235
FIGURE 27- RFDL NORMAL DATAAND ABORT SEQUENCE ..................... 236
FIGURE 28- RFDL FIFO OVERRUN.............................................................. 237
FIGURE 29- XFDL NORMAL DATA SEQUENCE........................................... 238
FIGURE 30- XFDL UNDERRUN SEQUENCE ............................................... 239
FIGURE 31- J2 FRAMER EXAMPLE............................................................. 240
FIGURE 32- BOUNDARY SCAN ARCHITECTURE....................................... 242
FIGURE 33- TAP CONTROLLER FINITE STATE MACHINE......................... 244
FIGURE 34- INPUT OBSERVATION CELL (IN_CELL).................................. 248
FIGURE 35- OUTPUT CELL (OUT_CELL) .................................................... 248
FIGURE 36- BIDIRECTIONAL CELL (IO_CELL) ........................................... 249
FIGURE 37- LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS249
FIGURE 38- MICROPROCESSOR READ ACCESS TIMING........................ 256
FIGURE 39- MICROPROCESSOR WRITE ACCESS TIMING ...................... 258
FIGURE 40- XCLK INPUT TIMING FOR JITTER ATTENUATION................. 260
FIGURE 41- TCLKI INPUT TIMING ............................................................... 262
FIGURE 42- DIGITAL RECEIVE INTERFACE INPUT TIMING DIAGRAM..... 263
FIGURE 43- TRANSMIT DATA LINK INPUT TIMING DIAGRAM................... 265
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
xii
PMC [ PMC-SIERRA, INC ]
