PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
The receive ATM cell processor section:
• Provides ATM framing using cell delineation.
• Provides cell descrambling, header check sequence (HCS) error detection,
idle/unassigned cell filtering, and accumulates the number of received
idle/unassigned cells, the number of received cells written to the FIFO, and
the number of HCS errors.
• Provides a four cell FIFO for rate decoupling between the line, and a higher
layer processing entity.
• Provides a synchronous 8-bit wide FIFO with receive byte parity generation
and timing compatible with the Saturn Compatible Interface Specification
(SCI-PHYTM) for multi-PHY interfaces.
• All four receive ATM cell processors are serviced via a single 8-bit wide multi-
PHY interface.
The transmit ATM cell processor section:
• Provides optional ATM cell scrambling, HCS generation/insertion,
programmable idle/unassigned cell insertion, diagnostics features and
accumulates transmitted cells read from the FIFO.
• Provides a four cell FIFO for rate decoupling between the line, and a higher
layer processing entity.
• Provides a synchronous 8-bit wide FIFO with transmit byte parity checking
and timing compatible with the Saturn Compatible Interface Specification
(SCI-PHYTM) for multi-PHY interfaces.
• All four transmit ATM cell processors are serviced via a single 8-bit wide
multi-PHY interface.
Loopback features:
• Provides for DS1 or E1 line loopback, payload loopback, or diagnostic
loopback.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
5
PMC [ PMC-SIERRA, INC ]
