PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
A Saturn Compatible Interface (SCI-PHYTM) FIFO is provided. This synchronous
FIFO accepts a read clock (RFCLK) and read enable signal from the MPHY
block. The receive FIFO output bus is tristated when the read enable is inactive.
The interface indicates the start of a cell (RSOC) and the receive cell available
status (RCA) when data is read from the receive FIFO (using the rising edges of
RFCLK while read enable is active). The RCA status changes from available to
unavailable when the FIFO is 4 byte read accesses away from being empty (or
when the FIFO is empty, when REMPTY4 is logic 0).
This RXFF indicates FIFO overruns using a maskable interrupt and register bits.
The FIFO is reset on FIFO overrun, causing up to 4 cells to be lost.
9.18 Transmit ATM Cell Processor (TXCP)
The Transmit Cell Processor (TXCP) Block integrates circuitry to support ATM
cell payload scrambling, header check sequence (HCS) generation, and
idle/unassigned cell generation.
The TXCP scrambles the cell payload field using the self synchronizing
scrambler with polynomial x43 + 1. The header portion of the cells is not
scrambled. Note that cell payload scrambling is optional in the S/UNI-MPH.
The HCS is generated using the polynomial, x8 + x2 + x + 1. The coset
polynomial x6 + x4 + x2 + 1 is added (modulo 2) to the calculated HCS octet as
required by the ATM Forum UNI specification, and ITU-T Recommendation I.432.
The resultant octet optionally overwrites the HCS octet in the transmit cell.
When the transmit FIFO is empty, the TXCP inserts idle/unassigned cells. The
idle/unassigned cell header is fully programmable using five internal registers.
Similarly, the 48 octet information field is programmed with an 8 bit repeating
pattern using an internal register. The TXCP accumulates the number of
transmitted assigned cells in a saturating counter.
For T1/E1 formats, the cell octets are byte aligned with the transmission
overhead (the framing bit for the T1 format, and timeslots 0/16 for the E1 format).
For arbitrary bit rate interfaces, the cell octets are optionally aligned to the
overhead indication signal (TOHI).
9.19 Transmit ATM 4 Cell FIFO (TXFF)
The Transmit FIFO (TXFF) provides FIFO management and the S/UNI-MPH
transmit cell interface. The transmit FIFO can hold up to four cells. The FIFO
depth may be programmed to one, two, three, or four cells. The FIFO provides
the cell rate decoupling function between the transmission system physical layer
and the ATM layer.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
