PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
9.16 Receive ATM Cell Processor (RXCP)
The Receive ATM Cell Processor (RXCP) Block integrates circuitry to support
cell delineation, cell payload descrambling, header check sequence (HCS)
verification and idle/unassigned cell filtering.
The RXCP cell delineates the framed T1 or E1 cell streams. Overhead bits (the
framing bit for T1 interfaces, or timeslots 0 and 16 for E1 interfaces) are
indicated by the FRMR block. Overhead bits in arbitrary rate interfaces are
indicated by the ROHM input.
Cell delineation is the process of framing to ATM cell boundaries using the
header check sequence (HCS) field found in the ATM cell header. The HCS is a
CRC-8 calculation over the first 4 octets of the ATM cell header. When
performing delineation, correct HCS calculations are assumed to indicate cell
boundaries.
The RXCP performs a sequential bit by bit hunt for a correct HCS sequence.
While performing this hunt, the cell delineation state machine is in the HUNT
state. When a correct HCS is found, the RXCP locks on the particular cell
boundary and enters the PRESYNC state. This state verifies that the previously
detected HCS pattern was not a false indication. If the HCS pattern was a false
indication then an incorrect HCS should be received within the next DELTA cells.
At that point a transition back to the HUNT state is executed. If an incorrect HCS
is not found in the PRESYNC state then a transition to the SYNC state is made.
In this state synchronization is not relinquished until ALPHA consecutive incorrect
HCS patterns are found. In such an event a transition is made back to the
HUNT state. The state diagram of the cell delineation process is shown in Figure
15.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
55
PMC [ PMC-SIERRA, INC ]
