PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Pin Name
Type
Pin Function
No.
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
I/O
17
16
15
14
13
12
11
10
Bidirectional Data Bus (D[7:0]). This bus is used
during S/UNI-MPH read and write accesses.
RDB
WRB
ALE
Input
Input
Input
112 Active low Read Enable (RDB). This signal is
pulsed low to enable a S/UNI-MPH register read
access. The S/UNI-MPH drives the D[7:0] bus
with the contents of the addressed register while
RDB and CSB are both low.
111 Active low Write Strobe (WRB). This signal is
pulsed low to enable a S/UNI-MPH register write
access. The D[7:0] bus is clocked into the
addressed register on the rising edge of WRB
while CSB is low.
114 Address Latch Enable (ALE). This signal latches
the address bus contents, A[10:0], when low,
allowing the S/UNI-MPH to be interfaced to a
multiplexed address/data bus. When ALE is
high, the address latches are transparent. ALE
has an integral pull-up resistor.
RSTB
Input
Input
110 Active low Reset (RSTB). This signal is set low
to asynchronously reset the S/UNI-MPH. RSTB
is a Schmitt-trigger input with an integral pull-up
resistor.
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
117 Address Bus (A[10:0]). This bus selects specific
118 registers during S/UNI-MPH register accesses.
119
120
121
122
123
124
125
126
127
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
36
PMC [ PMC-SIERRA, INC ]
