PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Figure 39
- Microprocessor Write Access Timing
A[10:0]
Valid Address
tS
tH
ALW
ALW
tV
L
tS
tH
LW
LW
ALE
(CSB+WRB)
D[7:0]
tS
tV
tS
tH
AW
AW
WR
tH
DW
DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1. A valid write cycle is defined as a logical OR of the CSB and the WRB
signals.
2. Microprocessor Interface timing applies to normal mode register accesses
only.
3. In non-multiplexed address/data bus architectures, ALE can be held high,
parameters tS
, tH
, tV , tS , and tH
are not applicable.
ALW
ALW
L
LW
LW
4. Parameters tH
and tS
are not applicable if address latching is used.
AW
AW
5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
6. When a set-up time is specified between an input and a clock, the set-up
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
258
PMC [ PMC-SIERRA, INC ]
