PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Figure 38
- Microprocessor Read Access Timing
tS
AR
A[10:0]
ALE
Valid
Address
tH
AR
tS
ALR
tV
tH
L
ALR
tH
tS
LR
LR
(CSB+RDB)
INTB
tP
INTH
tZ
tP
RD
RD
Valid Data
D[7:0]
Notes on Microprocessor Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 100 pF load on the
Microprocessor Interface data bus, (D[7:0]).
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
256
PMC [ PMC-SIERRA, INC ]
