PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
4. Microprocessor Interface timing applies to normal mode register accesses
only.
5. When a set-up time is specified between an input and a clock, the set-up
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
6. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
7. In non-multiplexed address/data bus architectures ALE can be held high;
parameters tS
, tH , tV , tS , and tH are not applicable.
ALR ALR L LR LR
8. Parameter tH is not applicable when address latching is used.
AR
Table 7
Symbol
- Microprocessor Write Access (Figure 39)
Parameter
Min
Max
Units
ns
tS
tS
tS
Address to Valid Write Set-up Time 10
AW
Data to Valid Write Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
20
10
10
20
0
ns
DW
ALW
ns
tH
ns
ALW
tV
tS
ns
L
Latch to Write Set-up
ns
LW
tH
tH
tH
Latch to Write Hold
5
ns
LW
DW
AW
WR
Data to Valid Write Hold Time
Address to Valid Write Hold Time
Valid Write Pulse Width
5
ns
5
ns
tV
40
ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
257
PMC [ PMC-SIERRA, INC ]
