PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Registers 020H, 120H, 220H and 320H: E1-FRMR Frame Alignment Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CRCEN
Reserved
AFAA
CHKSEQ
Reserved
REFR
0
0
0
0
0
0
0
0
REFCRCE
REFRDIS
These registers select the various framing formats and framing algorithms
supported by the E1-FRMR blocks.
Reserved:
The reserved bits must be programmed to logic 0 for correct operation.
CRCEN:
The CRCEN bit enables the E1-FRMR to frame to the CRC multiframe.
When the CRCEN bit is logic 1, the E1-FRMR searches for CRC multiframe
alignment and monitors for errors in the alignment. A logic 0 in the CRCEN
bit position disables searching for multiframe and suppresses the OOCMF,
CRCE, CMFER, and FEBE E1-FRMR statuses, forcing them to logic 0.
AFAA:
The AFAA bit enables an alternate framing algorithm. If AFAA is a logic zero,
frame alignment is declared after a correct FAS, a logic 1 in bit 2 of time slot
0 of the next frame and finally another FAS in the third frame are found. If
one of the conditions fails, the next bit position is checked for valid framing. If
AFAA is a logic one, the framing is similar to the above, but adds a "hold-off"
feature. If bit2 or the second 7-bit FAS conditions fail, the same byte location
is checked again in the subsequent frames before checking the next bit
position for frame alignment.
CHKSEQ:
The CHKSEQ bit enables the use of the check sequence to verify the correct
frame alignment in the presence of random imitative frame alignment signals.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
116
PMC [ PMC-SIERRA, INC ]
