PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
be jitter-free. When OCLKSEL is set to logic 0, the DJAT FIFO output clock is
driven with an internal jitter attenuated bit rate clock (1.544 MHz for T1 or
2.048 MHz for E1). FIFOBYP must be set to logic 1 if OCLKSEL is set to
logic 1.
TREF[1:0]:
The TREF[1:0] bits select the transmit reference clock source as shown in the
following table.:
TREF1
TREF0
Transmit Reference Source
0
0
0
1
TCLKI input.
Receive clock output (RCLKO) as selected by
the RCLK[1:0] bits in the Source
Selection/Interrupt ID register.
1
1
0
1
Receive clock from the RCLKI[x] input or
recovered from the RDP[x]/RDN[x] inputs.
XCLK input divided by 8 or by 24 depending
on the setting of the XCLKSEL bit.
Upon reset of the S/UNI-MPH, these bits are set to zero, selecting digital jitter
attenuation with TCLKO[x] referenced to TCLK. Figure 17 illustrates the various
bit setting options, with the reset condition highlighted.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
84
PMC [ PMC-SIERRA, INC ]
