PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Figure 17
- Transmit Timing Options
FIFO output
data clock
TCLKO[x]
DJAT
FIFO
FIFO input
data clock
OCLKSEL or FIFOBP or
MODE[1] (register X01H).
Reference clock to
Transmitter
blocks
0
1
*setting LINELB or
PAYLB automatically
selects TREF[1:0] =
10B.
TCLKI
RCLKO
00
DJAT
PLL
01
"Jitter Attenuated" Clock
RCLK[x]
10
TREF[1:0]
24x reference clock for jitter attenuation
11
÷ 8
XCLK
(24x or 8x)
÷ 3
0
"High-speed" clock for CDRC &
T1-FRMR
1
XCLKSEL
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
85