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PM7340 参数 Datasheet PDF下载

PM7340图片预览
型号: PM7340
PDF下载: 下载PDF文件 查看货源
内容描述: S / UNI ATM反向多路复用, 8个环节 [S/UNI INVERSE MULTIPLEXING FOR ATM, 8 LINKS]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 334 页 / 2670 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7340 S/UNI-IMA-8  
PRELIMINARY  
INVERSE MULTIPLEXING OVER ATM  
DATA SHEET  
PMC-2001723  
ISSUE 3  
INVERSE MULTIPLEXING OVER ATM  
9.3 Transmit Slave Interface (UTOPIA L2 mode) (26 Signals)  
Pin Name  
Type  
Pin  
No.  
Function  
TCLK  
Input  
E19 The Transmit Clock (TCLK) signal is used to  
transfer cells across the ANY-PHY interface to the  
internal downstream cell buffers.  
The TCA output is updated on the rising edge of  
TCLK.  
The TENB, TSOC, TDAT[15:0], TPRTY, TADR[4:0]  
inputs are sampled on the rising edge of TCLK.  
The TCLK input must cycle at a 52 MHz or lower  
instantaneous rate.  
TCA  
Tristate  
Output  
L22 The Transmit Cell Available (TCA) is an active high  
signal that indicates the availability of space in the  
selected logical channel FIFO when polled using the  
TADR[4:0] signals.  
The S/UNI-IMA-8 drives TCS with the cell space  
availability status for the polled port one TCLK cycle  
after a valid TADR[4:0] address is sampled.  
The TCA output is high-impedance when not polled.  
The TCA output is updated on the rising edge of  
TCLK.  
TENB  
Input  
Input  
L20 The Transmit enable bar (TENB) is an active low  
signal that is used to indicate cell transfers to the  
internal cell buffers.  
The TENB input is sampled on the rising edge of  
TCLK.  
TADR[4]  
TADR[3]  
TADR[2]  
TADR[1]  
TADR[0]  
K21 The Transmit Address (TADR[4:0]) signals are  
K20 used to address logical channels for the purposes of  
J19 polling and device selection.  
J22  
The TADR[4:0] input bus is sampled on the rising  
J21  
edge of TCLK.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
24  
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