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PM7340 参数 Datasheet PDF下载

PM7340图片预览
型号: PM7340
PDF下载: 下载PDF文件 查看货源
内容描述: S / UNI ATM反向多路复用, 8个环节 [S/UNI INVERSE MULTIPLEXING FOR ATM, 8 LINKS]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 334 页 / 2670 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7340 S/UNI-IMA-8  
PRELIMINARY  
INVERSE MULTIPLEXING OVER ATM  
DATA SHEET  
PMC-2001723  
ISSUE 3  
INVERSE MULTIPLEXING OVER ATM  
Pin Name  
Type  
Pin  
No.  
Function  
RDAT[15]  
RDAT[14]  
RDAT[13]  
RDAT[12]  
RDAT[11]  
RDAT[10]  
RDAT[9]  
RDAT[8]  
RDAT[7]  
RDAT[6]  
RDAT[5]  
RDAT[4]  
RDAT[3]  
RDAT[2]  
RDAT[1]  
RDAT[0]  
Output  
U22 The Receive Cell Data (RDAT[15:0]) signals carry  
T22 the ATM cell words that have been read from the  
U19 S/UNI-IMA-8 internal cell buffers. When this  
R20 interface is operating in 8-bit mode, the data is  
R22 carried on RDAT[7:0].  
T19  
The RDAT[15:0] output bus is updated on the rising  
R19  
edge of RCLK.  
P20  
P21  
P22  
P19  
N20  
N21  
N22  
N19  
M20  
RPRTY  
Output  
M22 The Receive Parity (RPRTY) signal provides the  
parity (programmable for odd or even parity) of the  
RDAT[15:0] bus. When the interface is operating in  
8-bit mode, the parity is calculated over RDAT[7:0]  
The RPRTY output is updated on the rising edge of  
RCLK.  
9.1 Receive Slave ATM Interface (UTOPIA L2 mode) (26 Signals)  
Pin Name  
Type  
Pin  
No.  
Function  
RCLK  
Input  
T21  
The Receive Clock (RCLK) signal is used to  
transfer data blocks from the S/UNI-IMA-8 across  
the receive UTOPIA L2 interface.  
The RCA, RSOC, RDAT[15:0], and RPRTY outputs  
are updated on the rising edge of RCLK. The RENB  
and RADR[4:0] inputs are sampled on the rising  
edge of RCLK.  
The RCLK input must cycle at a 52 MHz or lower  
instantaneous rate.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
18  
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