PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x1C0 – 0x1CE: TCAS Link #0 to Link #7 Configuration
Bit
Type
Function
Default
15:3
Unused
Reserved
E1
X
0
0
0
2
1
0
R/W
R/W
R/W
CEN
This register configures the operational modes of transmit link #0 to link #7
(TSDATA[N] / TSCLK[N]; where 0 ≤ N ≤ 7=).
CEN
The channelize enable bit (CEN) configures link #N for channelized operation.
TSCLK[N] is held low during the T1 framing bit or the E1 framing byte. Thus,
on the first rising edge of TSCLK[N] after the extended low period, a
downstream block can sample the MSB of time-slot 1. When CEN is set low,
link #N is unchannelized and the E1 register bit is ignored. TSCLK[N] can be
gapped during non-data bytes, and all data bits are treated as a contiguous
stream without regard to time-slots.
E1
The E1 frame structure select bit (E1) configures link #N for channelized E1
operation when CEN is set high. TSCLK[N] is held low during the FAS and
NFAS framing bytes. The most significant bit of time-slot 1 is placed on
TSDATA[N] on the last falling edge of TSCLK[N] ahead of the extended low
period. Link data is present at time-slots 1 to 31. When E1 is set low and CEN
is set high, link #N is configured for channelized T1 operation. TSCLK[N] is
held low during the framing bit. The MSB of time-slot 1 is placed on
TSDATA[N] on the last falling edge of TSCLK[N] ahead of the extended low
period. Link data is present at time-slots 1 to 24. E1 is ignored when CEN is
set low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
148
PMC [ PMC-SIERRA, INC ]
