PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
11.4 SDRAM Configuration and Diagnostic access
Register 0x040: SDRAM Configuration
Bit
Type
Function
Default
15:12
11:1
0
Unused
REF_RATE [10:0]
SDRAM_EN
0
0
0
R/W
R/W
This register configures and enables the SDRAM interface.
SDRAM_EN
The SDRAM_EN enables the SDRAM interface. A transition from 0 to 1 starts
the SDRAM initialization procedure; this procedure takes 70 SYSCLK cycles.
Note that no other SDRAM accesses are allowed during this period.
This SDRAM_EN is provided to ensure that the power-up of the SDRAM is
completed before the initialization sequence is applied. The power-up time is
controlled by SDRAM_EN. Typically, this must be at least 200 us. When
SDRAM_EN = ‘0’, no SDRAM accesses will take place and the chip will not
operate properly.
0) SDRAM accesses are disabled
1) SDRAM accesses are enabled
REF_RATE[10:0]
Defines the SYSCLK divide-down factor to determine the SDRAM refresh
rate. The REF_RATE must be configured prior to setting the SDRAM_EN. A
zero value will effectively disable refresh.
For Example, if the SDRAM requires 4K refreshes in 64 ms with a SYSCLK of
50 MHz, the REF_RATE should be programmed to:
Sys _Clk
(#_ of _ refresh)
50MHZ
REF _ RATE =
=
= 781 = 0x30D
4096
(
)
64ms
(time_ period)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
118
PMC [ PMC-SIERRA, INC ]
