S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
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In addition to the per-connection dual leaky bucket, provides a single leaky bucket UPC/NPC
function on a per-PHY basis. A programmable action (tag, discard or count only) may be
configured for each PHY policing device. Three programmable non-compliant cell or frame
counts are provided for each PHY. The non-compliant cell counts may be programmed to
count, for example, tagged CLP0 cells, dropped cells, and dropped CLP0 frames. Frame
counts are relevant either for GFR policing or for generic frame counting. The per-PHY
policing parameters and non-compliant cell counts are maintained in an on-chip RAM that
can be programmed and read via the 32-bit general purpose microprocessor interface.
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Allows groups of F5 connections to be policed in aggregate at the F4 level instead of at the
F5 level, through the use of the VP_POLICE bit.
Provides OAM-Fault Management on a per-connection basis. Simultaneous segment and
end-to-end F4 and F5 AIS, RDI and CC cell generation, termination and monitoring is
supported. Alarm bits and interrupt masks are provided on a per-connection basis. F4 to F5
AIS alarm splitting and F5 to F4 aggregation are provided. Paced insertion of FM cells is
provided.
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Allows OAM-Loopback address identification, termination, and loopback to be per-
connection configurable. Loopback cells may also be extracted to the microprocessor.
Provides a high-speed 32-bit microprocessor bus for configuration, control, and status
monitoring.
Provides a FIFO buffered cell insertion and extraction capability via the microprocessor bus
interface.
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Supports DMA access for cell extraction.
Uses up to 16 Mbit/s of external Pipelined ZBT SRAM (with or without parity) for
maintaining the data structure for the search tree. A 64 bit data + 8 bit parity 125 MHz bus
interface is used to connect to the external SRAM.
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Uses internal DRAM for maintaining VC context information.
Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
Low power 0.18 micron, 1.5 V CMOS technology with 2.5 V embedded DRAM, 2.5 V
external SRAM interface, and 3.3 V other external interfaces.
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768 Tape BGA package.
2.1
Policing
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Policing is performed for adherence to peak cell rate (PCR), cell delay variation (CDV),
sustained cell rate (SCR) and burst tolerance (BT). Violating cells can be dropped, tagged, or
just counted.
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Policing is performed using the virtual scheduling Generic Cell Rate Algorithm (GCRA)
described in ITU-T I.371.
GFR policing as described in ATM Forum TM 4.1 is provided, with enforcement of PCR,
MCR, CLP Conformance, and Maximum Frame Length.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
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PMC [ PMC-SIERRA, INC ]
