S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
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The Output interface supports a 32-bit 104 MHz UTOPIA Level 3 Link Layer (Master)
interface using Multi-PHY addressing with user-programmable weighted polling for up to
48 PHY queues on a single physical port. Extended ATM cell lengths of 52 to 64 bytes
are supported, with optional HEC/UDF, prepend, and postpend words. Mapping of
logical PHYs to physical PHYs is supported, to facilitate Automated Protection
Switching.
Alternately, the Input Interface supports a 32-bit 104 MHz POS-PHY Level 3 Tx PHY
Layer interface, capable of handling a mix of packets and ATM cells. Each of 48 PHY
queues on a single physical port must be set up to carry either packets or cells. Cells are
processed by S/UNI-ATLAS-3200, but packets are not processed and are buffered and
passed through transparently. In this case, the Output interface supports a 32-bit 104
MHz POS-PHY Tx Link Layer interface.
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Is compatible with a wide range of switching fabrics and traffic management architectures
including per-VC or per-PHY queuing.
Contains a highly-flexible CAM-type cell and connection identification, which can use
arbitrary PHYID/VPI/VCI values and/or cell appended bytes for connection identification in
both directions. 34-bits of discrimination allows the entire PHYID/VPI/VCI address range to
be resolved.
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Includes header translation functions, permitting the translation of the VPI, VCI, and/or cell
appended bytes. Information about the cell and connection type can be included in appended
bytes in order to aid downstream processing.
Provides comprehensive cell processing functionality, which includes a highly flexible search
engine that covers the entire PHYID/VPI/VCI address range, programmable dual leaky
bucket UPC/NPC, per-connection CLP0 and CLP1 cell counts (programmable), OAM-PM
termination, generation and monitoring, OAM-FM termination, generation and alarm
generation (monitoring), and OAM-LB address matching, termination, and loopback.
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Provides a Count Rollover FIFO greatly, which reduces the need to poll internal counts.
Provides available AAL5 Frame counting via the policing counts.
Provides per-PHY output buffering, which resolves head-of-line blocking issues.
Provides a UPC/NPC function, which is a programmable dual leaky bucket policing device
with a programmable action (tag, discard, or count only) for each bucket. A total of 3
programmable 16-bit non-compliant cell counts are provided. The non-compliant cell counts
may be programmed to count, for example, dropped CLP0 cells, dropped CLP1 cells, and
tagged CLP0 cells. The UPC/NPC function also has a continuously violating mode, where a
programmable action is taken on all cells regardless of their compliance.
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Provides guaranteed Frame Rate policing, including AAL5 partial packet discard, so that the
remainder of an AAL5 packet can be discarded if a single cell in the packet is discarded as a
result of violating policing. AAL5 packets may also be completely tagged or discarded as
appropriate. GFR policing is selectable on a per-connection basis.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
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PMC [ PMC-SIERRA, INC ]
