S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Reserved
This bit must be programmed to logic 0.
VCRA[15:0]
This register holds the VC Record Address to be used to address the VC Table internal
DRAM through Microprocessor initiated accesses. It identifies the desired VC Table entry.
DRAM_CRC_ERR
When this bit is logic 1, then the CRC of the VC being read was incorrect. This bit is valid
after a read or write request has been made and the BUSY bit has gone low. This bit is valid
either on a read, or on a write (if any of the Write Mask bits are logic 0). Because write or a
clear-on-read operation will correct the DRAM CRC, it is important that the status of this bit
be checked.
CC_CLRONRD
If CC_CLRONRD is logic 1, then after a read access, the Cell Count fields of the VC table
are automatically written to all ‘0’. Other bits in the table are preserved in the write back.
If CC_CLRONRD = ‘0’, no write back to clear the count bits is initiated.
AC_CLRONRD
If AC_CLRONRD is logic 1, then after a read access, the Alternate Cell Count fields of the
VC table are automatically written to all ‘0’. Other bits in the table are preserved in the write
back.
If AC_CLRONRD = ‘0’, no write back to clear the count bits is initiated.
NCC_CLRONRD
If NCC_CLRONRD is logic 1, then after a read access, the Non-Compliant Count fields of
the VC table are automatically written to all ‘0’. Other bits in the table are preserved in the
write back.
If NCC_CLRONRD = ‘0’, no write back to clear the count bits is initiated.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
227
PMC [ PMC-SIERRA, INC ]
