S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
BUSY
The BUSY bit is high while a Microprocessor initiated access request to the DRAM is
pending. This register should be polled until the BUSY bit goes low before another
microprocessor access request is initiated. A microprocessor access request will be
completed within 220 SYSCLK cycles. If the STANDBY bit in the S/UNI-ATLAS-3200
Master Configuration register is a logic 1, the access time is reduced to less than 22 SYSCLK
cycles.
RWB
The RWB bit selects the operation to be performed on the addressed VC Table: when RWB is
set to a logic 1, a read from the DRAM is requested; when RWB is set to a logic 0, a write to
the DRAM is requested.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
228
PMC [ PMC-SIERRA, INC ]
