S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Table 34 Change of State FIFO ....................................................................................129
Table 35 Count Rollover FIFO Format For Per-VC Count Entries................................131
Table 36 Count Rollover FIFO Format For Per-PHY Count Entries .............................131
Table 37 Count Rollover FIFO Format For PM Entries.................................................132
Table 38 Backwards Cell Interface Cell Format............................................................136
Table 39 BCIF Cell Information Field ............................................................................137
Table 40 Microprocessor Cell Information Field............................................................141
Table 41 Suggested FIFO Size Encoding.....................................................................329
Table 42 Suggested FIFO Size Encoding.....................................................................360
Table 43 Suggested FIFO Size Encoding.....................................................................371
Table 44 Test Mode Register Memory Map..................................................................376
Table 45 Test Mode 0 Read Map..................................................................................378
Table 46 Test Mode 0 Write Map..................................................................................379
Table 47 Instruction Register ........................................................................................380
Table 48 Identification Register.....................................................................................380
Table 49 Boundary Scan Register ................................................................................380
Table 50 Suggested FIFO Size Encoding.....................................................................390
Table 51 SDQ-ATLAS Configuration Example .............................................................391
Table 52 Absolute Maximum Ratings............................................................................418
Table 53 DC Characteristics .........................................................................................419
Table 54 RTSB AC Timing............................................................................................421
Table 55 Half-Second Clock AC Timing........................................................................421
Table 56 Microprocessor Interface Read Access AC Timing .......................................421
Table 57 Microprocessor Interface Write Access AC Timing........................................423
Table 58 UTOPIA Level 3 / POS-PHY Level 3 AC Timing............................................424
Table 59 BCIF Interface AC Timing ..............................................................................425
Table 60 SRAM Interface AC Timing ............................................................................426
Table 61 JTAG Port Interface Timing............................................................................426
Table 62 Ordering Information ......................................................................................429
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
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PMC [ PMC-SIERRA, INC ]
