S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Figure 34 TxPhy POS-PHY Packet Transfer ................................................................405
Figure 35 Transmit POS-PHY ATM Cell Transfer.........................................................406
Figure 36 TxLink POS-PHY Logical Timing..................................................................407
Figure 37 TxLink POS-PHY ATM Cell Transfer Timing ................................................408
Figure 38 Ingress UTOPIA Logical Timing....................................................................409
Figure 39 RxLink UTOPIA Cell Transfer.......................................................................410
Figure 40 RxLink Back-to-Back UTOPIA Cell Transfers...............................................410
Figure 41 RxPhy UTOPIA Cell Transfer .......................................................................411
Figure 42 Egress UTOPIA Logical Timing ....................................................................412
Figure 43 TxPhy UTOPIA Cell Transfer........................................................................413
Figure 44 TxLink UTOPIA Transfer...............................................................................414
Figure 45 TxLink Back-to-Back UTOPIA Transfer ........................................................414
Figure 46 Interface between S/UNI-ATLAS-3200 and External RAM...........................416
Figure 47 SRAM Interface Functional Timing ...............................................................416
Figure 48 Normal BCIF Functional Timing....................................................................417
Figure 49 IBCIF as Tx Slave Functional Timing............................................................417
Figure 50 RSTB AC Timing...........................................................................................421
Figure 51 Half-Second Clock AC Timing ......................................................................421
Figure 52 Microprocessor Interface Read Access AC Timing ......................................422
Figure 53 Microprocessor Interface Write AC Timing ...................................................424
Figure 54 UTOPIA Level 3 / POS-PHY Level 3 AC Timing ..........................................425
Figure 55 BCIF Interface AC Timing .............................................................................425
Figure 56 SRAM Interface AC Timing...........................................................................426
Figure 57 JTAG Port Interface AC Timing ....................................................................428
Figure 58 768 Tape Ball Grid Array (TBGA) .................................................................430
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
19
PMC [ PMC-SIERRA, INC ]
