RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
3. The maximum frequency per line in low speed mode is 15 MHz. However
aggregate speed for all lines within an A1SP must be 20 MHz or less with a
SYS_CLK of 38.88 MHz.
16.8.1.2
Receive
Table 40 Receive Low Speed Interface Timing
Symbol
Description
Min Max Units
f
RL_CLK Frequency (See note 3)
RL_CLK Duty Cycle
0
15
60
MHz
%
R
d
40
10
R
tS
Input Set-up time to falling edge of
RL_CLK
ns
tH
Input Hold time from falling edge
RL_CLK
10
ns
Notes on Receive Low Speed Timing:
1. Inputs are expected to be driven using the rising edge of RL_CLK.
2. Inputs are latched using the falling edge of RL_CLK.
3. The maximum frequency per line in low speed mode is 15 MHz. However
aggregate speed for all lines must be 20 MHz or less with a SYS_CLK of
38.88 MHz.
4. For applications which use SRTS clock recovery, the RL_CLK must not be a
gapped clock and jitter should be less than .3 UI.
Figure 131 Receive Low Speed Interface Timing
RL_CLK
tS
tH
RL_DATA
RL_SIG
RL_SYNC
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