RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
16.8.3.2
Receive
Table 44 Receive High Speed Interface Timing
Symbol
Description
Min Max Units
f
RL_CLK0 Frequency
RL_CLK0 Duty Cycle
0
45
60
MHz
%
R
d
40
5
R
tS
Input Set-up time to falling edge of
RL_CLK0
ns
tH
Input Hold time from falling edge
RL_CLK0
1
ns
Notes on Receive High Speed Timing:
1. Inputs are latched using the falling edge of RL_CLK.
2. The maximum frequency per line in High Speed mode is 45 MHz when
SYS_CLK is 38.88 MHz. However if SYS_CLK is 45 MHz then the maximum
frequency for RL_CLK0 is 52 MHz.
3. For applications which use SRTS clock recovery, the RL_CLK must not be a
gapped clock and jitter should be less than .3 UI.
Figure 135 Receive High Speed Interface Timing
RL_CLK0
tS
tH
RL_DATA0
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
353
PMC [ PMC-SIERRA, INC ]
