RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
6
DESCRIPTION
The AAL1gator-8 AAL1 Segmentation And Reassembly (SAR) Processor
is a monolithic single chip device that provides DS1, E1, E3, or DS3 line
interface access to an ATM Adaptation Layer One (AAL1) Constant Bit
Rate (CBR) ATM network. It arbitrates access to an external SRAM for
storage of the configuration, the user data, and the statistics. The device
provides a microprocessor interface for configuration, management, and
statistics gathering. PMC-Sierra also provides a software device driver for
the AAL1gator-8 device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
32
PMC [ PMC-SIERRA, INC ]
