RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
5
BLOCK DIAGRAM
The AAL1gator-8 contains an AAL1 SAR Processor (A1SP) which
performs the segmentation and re-assembly of the AAL1 cells. The A1SP
block interfaces to a common UTOPIA interface on one side and a line
Interface block on the other side, which can be configured to support
several different line protocols. The A1SP block connects to the RAM
interface. The processor interface block, which also contains the external
clock control interface, is shared by all blocks. The AAL1gator-8 supports
8 serial lines.
Figure 3
- AAL1gator-8 Internal Block Diagram
Clock
MUX
Line Interface
RSTB
SCAN_ENB
SCAN_MODEB
TATM_DATA[15:0]
TATM_PAR
8
F0B
TATM_ENB
TATM_SOC
TATM_CLAV
TATM_CLK
RPHY_ADD[4:0]
H-MVIP
2
8
8
A1SP
TL_DATA[7:0]
TL_SYNC[7:0]
TL_SIG[7:0]
RL_DATA[7:0]
RL_SYNC[7:0]
RL_SIG[7:0]
UTOPIA
Interface
8
8
Direct
RATM_DATA[15:0]
RATM_PAR
RATM_ENB
LINE_MODE
RATM_SOC
RATM_CLAV
RATM_CLK
TPHY_ADD[4:0]
RAM
Interface
Processor
Interface
External Clock
Interface
JTAG
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
31
PMC [ PMC-SIERRA, INC ]
