RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x80030 : A1SP Clock Configuration Register (A_CLK_CFG)
Bit
Type
Function
Default
15:10
9
R
Unused
X
0
R/W
R/W
R/W
NCLK_DIV_EN
NCLK_DIV
8:5
4:0
0000B
00000B
ADAP_FILT_SIZE
ADAP_FILT_SIZE
When a line is configured to use the internal adaptive clocking algorithm, this
field defines the size of the filtering window. The filter size is a power of 2
where ADAP_FILT_SIZE represents the exponent (ie, 2ADAP_FILT_SIZE). The
adaptive algorithm determines the clock frequency by averaging the byte
difference over 2ADAP_FILT_SIZE number of samples. The maximum value is
“10000”B or 16.
NCLK_DIV
When NCLK_DIV_EN is set, this field indicates how much to divide down the
NCLK for the A1SP. The clock is divided by ((NCLK_DIV + 1) *2). For
instance if this field is 000 and NCLK_DIV_EN = ‘1’ then the NCLK is divided
by 2: If this field is “1111” then NCLK is divided by 32.
NCLK_DIV_EN
When set the NCLK is divided down as specified by the NCLK_DIV field.
Otherwise the NCLK is passed directly from the NCLK pin to the A1SP.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
243
PMC [ PMC-SIERRA, INC ]
