RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Table 16 Register Memory Map
Address
Register Description
0x8000X
0x8010X
Command Registers
Ram Interface Registers
0x8012X
UTOPIA Interface Registers
Line Interface Registers
0x80200-0x80FFF
0x81000-0x812FF
0x82000-0x82FFF
0x84000-0x84FFF
Interrupt and Status Registers
Idle Channel Configuration and Status Registers
DLL Control and Status Registers
11.1 Command Registers
These registers provide the means to update line and chip configuration from
memory, reset unused lines, and send OAM cells. The register to add queues is
also located here. There is one register per A1SP block.
Table 17 Command Register Memory Map
Address
Register Description
Reset and Device ID
Register Mnemonic
0x80000
0x80010
0x80020
0x80030
DEV_ID_REG
A_CMD_REG
A_ADDQ_FIFO
A_CLK_CFG
Command Register for A1SP
Add Queue FIFO Register for A1SP
Clock Configuration for A1SP
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