PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
4.2.2 Pinout Table
Table 5 shows the pinout for the AAL1gator II.
Table 5. AAL1gator II Pinout
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VDD
VDD
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
SRTS_LINE(2)
SRTS_LINE(1)
SRTS_LINE(0)
SRTS_STRB
ADAP_STRB
GND
77
78
RL_SER(1)
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
TL_CLK(4)
GND
2
RL_SIG(1)
TLCLK_OUTPUT_EN
TL_SIG(2)
TL_SER(2)
TL_MSYNC(2)
TL_FSYNC(2)
TL_CLK(2)
GND
3
RATM_DATA(7)*
RATM_DATA(6)*
RATM_DATA(5)*
RATM_DATA(4)*
RATM_DATA(3)*
RATM_DATA(2)*
RATM_DATA(1)*
RATM_DATA(0)*
RATM_SOC*
/RATM_EMPTY*
/RATM_EN*
79
RL_CLK(4)
RL_FSYNC(4)
GND
4
80
5
81
6
82
GND
7
N_CLK
83
VDD
8
GND
84
VDD
9
SRTS_LINE(3)
VDD
85
RL_MSYNC(4)
RL_SER(4)
RL_SIG(4)
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
86
RL_CLK(2)
GND
TL_SIG(0)
TL_SER(0)
TL_MSYNC(0)
TL_FSYNC(0)
GND
87
88
GND
89
SYS_CLK
GND
TL_SIG(5)
TL_SER(5)
TL_MSYNC(5)
TL_FSYNC(5)
TL_CLK(5)
GND
/RPHY_ADDR
GND
90
91
NC
RATM_CLK*
GND
TL_CLK(0)
GND
92
VDD
93
VDD
/TPHY_ADDR
VDD
PHY_ENABLE
VDD
94
RL_FSYNC(2)
RL_MSYNC(2)
RL_SER(2)
RL_SIG(2)
NC
95
RL_CLK(5)
RL_FSYNC(5)
RL_MSYNC(5)
RL_SER(5)
RL_SIG(5)
NC (Must be left disconnected)
TL_SIG(6)
TL_SER(6)
TL_MSYNC(6)
TL_FSYNC(6)
TL_CLK(6)
GND
TATM_CLK*
GND
RL_CLK(0)
GND
96
97
/TATM_EN*
GND
98
/TATM_FULL*
TATM_SOC*
TATM_DATA(7)*
TATM_DATA(6)*
TATM_DATA(5)*
TATM_DATA(4)*
GND
VDD
99
TL_SIG(3)
TL_SER(3)
TL_MSYNC(3)
TL_FSYNC(3)
TL_CLK(3)
GND
VDD
100
101
102
103
104
105
106
107
108
109
110
111
RL_FSYNC(0)
RL_MSYNC(0)
RL_SER(0)
RL_SIG(0)
NC
RL_CLK(3)
RL_FSYNC(3)
RL_MSYNC(3)
RL_SER(3)
RL_SIG(3)
NC
TATM_DATA(3)*
VDD
TL_SIG(1)
TL_SER(1)
TL_MSYNC(1)
TL_FSYNC(1)
TL_CLK(1)
GND
RL_CLK(6)
RL_FSYNC(6)
RL_MSYNC(6)
RL_SER(6)
RL_SIG(6)
TATM_DATA(2)*
TATM_DATA(1)*
TATM_DATA(0)*
SRTS_DOUT(3)
TL_SIG(4)
ꢆꢈ
PMC [ PMC-SIERRA, INC ]
