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PM73121-RI 参数 Datasheet PDF下载

PM73121-RI图片预览
型号: PM73121-RI
PDF下载: 下载PDF文件 查看货源
内容描述: AAL1分段重组处理器 [AAL1 Segmentation And Reassembly Processor]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 223 页 / 2148 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM73121AAL1gator II  
Data Sheet  
PMC-Sierra, Inc.  
PMC-980620  
,VVXHꢀꢁ  
AAL1 SAR Processor  
From Version  
To Version  
Major Changes  
Changed from WAC-121-A to PM73121.  
04/17/98  
Issue 1  
Changed from User’s Manual to Long Form Data Sheet.  
Deleted references to the BT_Mode and default mode.  
Added PMC part numbers to Figure 5 on page 11, Figure 6 on  
page 12, Figure 7 on page 13, and Figure 86 on page 168.  
Under the “R_LINE_STATE Word Format” section on page 156,  
added “Not used in UDF-HS mode.” for the R_UNDERRUN and  
R_RESUME field descriptions.  
Under section 7.11 “Activating a New Queue on an Active Line”,  
on page 167, changed from “CMD_REG_ATTN” to  
“CSD_REG_ATTN bit”.  
01/21/98  
04/17/98  
Changed references from SRTS_PORT to SRTS_LINE  
throughout the manual.  
Added the sixth bullet on page 6.  
Under “Potential System Impacts” on page 7, added “Hardware  
Considerations”.  
Deleted the first paragraph on page 65.  
Replaced section 3.7.1 “SRTS for the Receive Side” starting on  
page 66 with section 3.7.1 “Generation of TL_CLK” starting on  
page 68.  
Added section 3.7.1.1 “Recovered Mode” starting on page 69,  
section 3.7.1.2 “Synthesize a Nominal E1 or T1 Clock” starting on  
page 69, and section 3.7.1.3 “Synthesize an E1 or T1 Clock based  
on SRTS” starting on page 70.  
In Table 9 on page 88, changed the last sentence of the  
“SYS_CLK” description to read “The maximum frequency is  
40 MHz.  
In Table 10 on page 89, added the note to the description of “/  
SCAN_TRST” on page 89.  
Under section 6.5 “RAM and Microprocessor Timing” starting on  
page 104, changed the first sentence of the third paragraph from  
“running at 38.88 MHz” to “running near maximum speed”.  
The first sentence of the fourth paragraph changed from  
“(38.88 MHz)” to “(40.00 MHz)”.  
In Figure 69 on page 105, changed SYS_CLK from “38.88 MHz”  
to “40.00 MHz”.  
In Table 21 on page 105, changed the maximum value of Number  
12 from “8” to “7”.  
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