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PM73121-RI 参数 Datasheet PDF下载

PM73121-RI图片预览
型号: PM73121-RI
PDF下载: 下载PDF文件 查看货源
内容描述: AAL1分段重组处理器 [AAL1 Segmentation And Reassembly Processor]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 223 页 / 2148 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM73121AAL1gator II  
Data Sheet  
PMC-Sierra, Inc.  
PMC-980620  
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AAL1 SAR Processor  
7.4.3 LIN_STR_MODE  
Organization: Eight words.  
Base address: 10h  
Index: 1h  
Type: Read/Write  
Function: Stores the per-line configuration.  
Format: Refer to the following table.  
Offset  
Name  
Description  
0h  
1h  
2h  
3h  
4h  
5h  
6h  
7h  
LIN_STR_MODE_0  
LIN_STR_MODE_1  
LIN_STR_MODE_2  
LIN_STR_MODE_3  
LIN_STR_MODE_4  
LIN_STR_MODE_5  
LIN_STR_MODE_6  
LIN_STR_MODE_7  
Line structure mode for line 0.  
Line structure mode for line 1.  
Line structure mode for line 2.  
Line structure mode for line 3.  
Line structure mode for line 4.  
Line structure mode for line 5.  
Line structure mode for line 6.  
Line structure mode for line 7.  
Field (Bits)  
Description  
HS_TX_COND  
(15)  
Send cells with all 1s when in high-speed mode (line 0 only).  
HS_RX_COND  
(14)  
Fetch receive conditioning data from the R_COND_DATA buffer for line 0, channels 0  
and 1. High-speed mode (line 0 only).  
T1_MODE  
(13)  
Determines mode of the line. This bit is valid only if the MIXED_MODE_EN bit in the  
COMP_LIN_REG is set.  
1
0
Line is in T1 mode.  
Line is in E1 mode.  
E1_WITH_T1_SIG  
(12)  
Enables T1 signaling while in E1 mode for this line. Signaling is updated every  
24 frames instead of every 16 frames. This bit is valid only when the line is in E1  
SDF-MF mode. AAL1 cell structures contain a signaling nibble every 25 bytes instead  
of every 17 bytes per single DS0.  
1
0
Use T1 signaling.  
Use E1 signaling.  
Not used  
(11:6)  
Write with a 0 to maintain future software compatibility.  
CLK_SOURCE  
(5:4)  
Selects TL_CLK source. This value will override the setting defined by the TLCLK_  
OUTPUT_EN input. If switching from an external to an internal clock or visa versa,  
make sure there are not two clocks driving simultaneously.  
00 Use external clock. (TL_CLK is an input).  
01 LOOPED - Use RL_CLK as the clock source.  
10 NOMINAL - Generate a clock of the nominal (T1 or E1) frequency from  
SYS_CLK.  
11 SRTS - Generate a clock frequency based on the received SRTS values.  
Not used  
(3)  
Write with a 0 to maintain future software compatibility.  
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