PMC-Sierra, Inc.
PM6541 E1XC-EVBD
TELECOM STANDARD PRODUCT
PMC-930917
ISSUE 1
E1XC EVALUATION DAUGHTERBOARD
3.2.1 External Signal Header
This header is provided to accept an external clock and framing pulse source. These
inputs are then buffered for use on the board. External clock sources must be
buffered through this header to avoid possible damage to the E1XCs or DPLL.
Signal
Type
Ref.
Description
EXTFP
I
J26-2 External Framing Pulse Input
J26-4 External Clock Input
EXTCLK
BEXTFP
BEXTCLK
I
O
O
J27-1 Buffered External Framing Pulse
J27-2 Buffered External Clock
3.2.2 DPLL Header
This header is provided to give access to the clock generating MT8940 DPLL chip
as well as provide direct oscillator access. All of the major DPLL outputs are brought
out to this header even though they may be of limited use with the E1XC (e.g. the
4.096 MHz clock).
Signal
FPIN
C8KB
GFP
Type Ref.
Description
I
J29-2
J29-1
J29-3
1.544 MHz Framing pulse input to MT8940.
2.048 MHz Framing pulse in/out (mode dependent).
I/O
I/O
8 kHz Framing pulse output from the MT8940. Note
that this active low output signal is derived from the
16.388 MHz clock and has a 244ns pulse width.
C1M5
C1M5B
C2M
O
O
O
O
O
O
J29-4
J29-5
J29-6
J29-7
J29-8
J29-9
1.544 MHz Output clock from MT8940.
Inverted C1M5 clock.
2.048 MHz output clock from MT8940.
Inverted C2M clock.
C2MB
C4M
4.096 MHz Output clock from MT8940.
Inverted C4M clock.
C4MB
8
PMC [ PMC-SIERRA, INC ]
