PMC-Sierra, Inc.
PM6541 E1XC-EVBD
TELECOM STANDARD PRODUCT
PMC-930917
ISSUE 1
E1XC EVALUATION DAUGHTERBOARD
AD[1]
AD[0]
PA3
I/O
C19
C20
C21
C22
C23
C24
C25
Multiplexed address/data bus bit 1
Multiplexed address/data bus bit 0
68HC11 Processor Port A bit 3
68HC11 Processor Port A bit 4
68HC11 Processor Port A bit 5
68HC11 Processor Port A bit 6
I/O
O
O
O
O
I
PA4
PA5
PA6
PD2
MISO. Master In Slave Out of Port D acting as SPI.
Pulled up on motherboard.
PD3
PD4
PD5
O
O
O
C26
C27
C28
MOSI. Master Out Slave In of Port D acting as SPI.
Pulled up on motherboard.
SCK. Serial clock of Port D acting as SPI. Pulled up
on motherboard.
SS. Slave Select of Port D acting as SPI active low.
Pulled up on motherboard.
IRQ
I
I
I
C29
C30
C31
Maskable interrupt
XIRQ
DISB
Non Maskable Interrupt
EVMB memory disable. Pulling this signal low will
disable MPU access to the EVMB's on-board RAM
and EPROM.
SP
O
O
C32
SPARE
Ground
GND
A1-
A28
+5V
O
A29-
A32
+5 Volts
3.2
Header Connections
All E1XC functional pins are connected to male header strips to provide as much
access as possible. These headers may be used as probe points or as a means to
build sample applications by making appropriate connections between points. Each
E1XC can run in isolation of the other, thus any application, other than the default
sample "CSU", will require header connections to be made.
7
PMC [ PMC-SIERRA, INC ]
