PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Figure 8
- DJAT JitterTolerance
100
40
35
DJAT
minimum
tolerance
10
Jitter
Amplitude,
UI pp
1.5
1.0
acceptable
CCITT G.823
unacceptable
Region
0.2
0.1
0.01
1
2.4k
18k
10k
100
1k
100k
10
2 0
Jitter Frequency, Hz
The accuracy of the XCLK frequency and that of the DJAT PLL reference input
clock used to generate the jitter-free TCLKO have an effect on the minimum jitter
tolerance. Given that the DJAT PLL reference clock accuracy can be ±103 Hz
from 2.048 MHz, and that the XCLK input accuracy can be ±100 ppm from
49.152 MHz, the minimum jitter tolerance for various differences between the
frequency of PLL reference clock and XCLK/24 are shown in Figure 9.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
56
PMC [ PMC-SIERRA, INC ]
