PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
timeslot in the E1 frame and output in PMC format. Both the output data stream
and the output signalling stream are compatible with the TRAN E1 Transmitter
block.
The SIGX provides user control over signalling freezing with a 95% confidence
level of freezing with valid signalling data for a 50% ones density out-of-frame
condition. The SIGX also provides control over timeslot data inversion, trunk
conditioning, and signalling debounce on a per-timeslot basis directly, via the
Common Bus Interface (CBI).
9.9
Backplane Receive Interface (BRIF)
The Backplane Receive Interface allows data to be presented to a backplane in a
2048 kbit/s serial stream, allows BPV transparency by outputting dual-rail data at
2048 kbit/s, and allows access to the recovered PCM stream (either the HDB3
decoded stream, or the undecoded stream) at 2048 kbit/s.
The block generates the output data stream on the BRPCM pin containing 32
timeslot bytes of data. The BRSIG output pin contains 30 bytes of signalling
nibble data located in the least significant nibble of each byte.The framing
alignment indication on the BRFPO pin can be configured to indicate the first bit
of each 256-bit frame, the first bit of the first frame of the CRC multiframe, the
first bit of the first frame of the signalling multiframe or all overhead bits.
9.10 Transmitter (TRAN)
The Transmitter function is provided by the TRAN block.
The TRAN generates a 2048 kbit/s data stream according to ITU-T
recommendations, providing individual enables for frame generation, CRC
multiframe generation, and channel associated signalling (CAS) multiframe
generation.
In concert with Transmit Per-Channel Serial Controller (TPSC), the TRAN block
provides per-timeslot control of idle code substitution, data inversion, digital
milliwatt substitution, selection of the signalling source and CAS data. All
timeslots can be forced into a trunk conditioning state (idle code substitution and
signalling substitution) by use of the master trunk conditioning bit in the
Configuration Register.
Common Channel Signalling (CCS) is supported in time slot 16 either through
the internal HDLC Transmitter (XFDL) or through a serial data input and clock
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
