PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
SIGX Indirect Registers 96 (60H) - 127 (7FH) - Segment 4:Typical
Per-Timeslot Configuration and SignallingTrunk Conditioning Data
Register
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RINV[1]
RINV[0]
RTKCE
RDEBE
A’
X
X
X
X
X
X
X
X
B’
C’
D’
RINV[1:0]:
The RINV[1:0] bits select whether the BRPCM stream is entirely or selectively
inverted. The bit mapping is as follows.
• 00 - do not invert
• 01 - invert even bits (2,4,6,8)
• 10 - invert odd bits (1,3,5,7)
• 11 - invert all bits
RTKCE:
The RTKCE bit enables per-timeslot data stream and signal stream trunk
conditioning. A logic 1 in this bit position enables trunk conditioning while a
logic 0 disables trunk conditioning. When RTKCE is enabled, per-timeslot
trunk conditioning data from one of the timeslot Trunk Conditioning Data
Registers (one of 40H to 5FH) is output onto the data stream, BRPCM. In
addition, the per-timeslot signalling trunk conditioning bits A’,B’,C’ and D’ are
output onto the signalling data stream, BRSIG.
RDEBE:
The RDEBE bit enables debouncing of timeslot signalling bits. A logic 1 in
this bit position enables signalling debouncing while a logic 0 disables it.
When debouncing is selected, per-timeslot signalling transitions are ignored
until two consecutive, equal values are sampled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
165
PMC [ PMC-SIERRA, INC ]
