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PM5381 参数 Datasheet PDF下载

PM5381图片预览
型号: PM5381
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN用户网络接口,用于2488 Mbit / s的 [SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S]
分类和应用: 网络接口
文件页数/大小: 487 页 / 2424 K
品牌: PMC [ PMC-SIERRA, INC ]
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PMC-Sierra, Inc.  
PRELIMINARY  
PM5381 S/UNI-2488  
DATASHEET  
PMC-2000489  
ISSUE 1  
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S  
Pin Name  
Type  
Pin  
No.  
Function  
TDI  
Input  
F27  
When the S/UNI-2488 is configured for JTAG operation, the  
test data input (TDI) signal carries test data into the  
S/UNI-2488 via the IEEE P1149.1 test access port. TDI is  
sampled on the rising edge of TCK. TDI has an integral pull  
up resistor.  
TDO  
Tristate  
Output  
D18  
D28  
The test data output (TDO) signal carries test data out of the  
S/UNI-2488 via the IEEE P1149.1 test access port. TDO is  
updated on the falling edge of TCK. TDO is a tri-state output  
which is inactive except when scanning of data is in progress.  
Schmidt  
TTL Input  
The active low test reset (TRSTB) signal provides an  
asynchronous S/UNI-2488 test access port reset via the IEEE  
P1149.1 test access port. TRSTB is a Schmidt triggered input  
with an integral pull up resistor. In the event that TRSTB is not  
used, it must be connected to RSTB.  
TRSTB  
9.9  
Analog Miscellaneous Signals (10)  
Pin Name  
Type  
Pin  
No.  
Function  
ATP[3]  
ATP[2]  
ATP[1]  
ATP[0]  
Analog  
AJ18  
AK18  
AG2  
AF3  
Four analog test ports (ATP[0], ATP[1], ATP[2], ATP[3]) are  
provided for production testing only. These pins must be tied  
to analog ground (AVS) during normal operation. ATP[1] and  
ATP[0] are the test ports for the 2488 Mbps analog circuitry,  
while ATP[3] and ATP[2] are the test ports for the 777.76 MHz  
LVDS analog circuitry.  
C0  
C1  
AH18  
AG18  
The analog C0 and C1 pins are provided for applications that  
must meet SONET/SDH jitter tolerance specifications. A 47nF  
non-polarized capacitor is attached across C0 and C1 for  
these applications.  
Analog  
When the capacitor is used, the RTYPE bit in the CRSI must  
be set to logic one for proper operation. When the  
capacitance is not used, these pins are left floating and the  
RYPE register must be set to logic zero for proper operation.  
C2  
C3  
AJ20  
AK20  
The analog C2 and C3 pins are provided for applications that  
must meet SONET/SDH jitter transfer specifications. A 4.7nF  
non-polarized capacitor is attached across C2 and C3 for  
these applications.  
Analog  
When the capacitance is not used, these pins are left floating.  
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use  
41  
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