PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Pin Name
Type
Input
Pin
No.
Function
APSIFP
P2
The APS input frame pulse signal (APSIFP) provides
system timing of the APS input serial interface. APSIFP is set
high once every 9720 APSIFPCLK cycles, or multiple thereof,
to indicate that the J0 frame boundary 8B/10B character has
been delivered on the differential LVDS bus (APSI+/-[4:1]).
APSIFP is sampled on the rising edge of APSIFPCLK+/-.
APSO+[4]
APSO-[4]
Analog
LVDS
Output
U1
U2
The differential APS output (APSO+/-[4:1]) serial data links
carries SONET/SDH OC-48 frame data to a mate in bit serial
format. Each differential pair carries a constituent OC-12 of
the data stream. Data on APSO+/-[4:1] is encoded in an
8B/10B format extended from IEEE Std. 802.3. The 8B/10B
character bit ‘a’ is received first and the bit ‘j’ is received last.
APSO+[3]
APSO-[3]
V3
V4
APSO+[2]
APSO-[2]
V1
V2
When in working mode as set using the APSMODE input, the
APSO+/-[4:1] signals carry the transmit data to the protect
mate. When in protect mode, the APSO+/-[4:1] signals carry
the receive data to the working mate.
APSO+[1]
APSO-[1]
W2
W3
The four differential pairs in APSO+/-[4:1] are frequency
locked but not phase locked. APSO+/-[4:1] are nominally
777.6 Mbps data streams.
APSOFP
Output
P1
The APS output frame pulse signal (APSOFP) provides
system timing of the APS output serial interface. APSOFP is
set high once every 9720 APSIFPCLK cycles, or multiple
thereof, to indicate that the J0 frame boundary 8B/10B
character has been delivered on the differential LVDS bus
(APSO+/-[4:1]).
APSOFP is updated on the rising edge of APSIFPCLK +/-.
APSIFPCLK
Input
P3
The APS input frame pulse clock (APSIFPCLK) provides a
jitter-free reference clock with which the APS input frame
pulse (APSIFP) is sampled. Also, the 777.76 MHz Clock
Synthesis Unit of the APS Port uses this clock as its
reference.
APSIFPCLK is expected to cycle at a 77.76 MHz rate, and
must be a derivative of REFCLK+/- to ensure that
APSIFPCLK is an exact divide-by-two in frequency compared
to REFCLK+/-.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
38
PMC [ PMC-SIERRA, INC ]
