PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
9.7
Microprocessor Interface Signals (37)
Pin Name
CSB
Type
Pin
No.
Function
Input
F4
The active low chip select (CSB) signal is low during S/UNI-
2488 register accesses.
Note that when not being used, CSB must be tied low. If CSB
is not required (i.e. register accesses controlled using the
RDB and WRB signals only), CSB must be connected to an
inverted version of the RSTB input.
The active low read enable (RDB) signal is low during a
S/UNI-2488 read access. The S/UNI-2488 drives the D[15:0]
bus with the contents of the addressed register while RDB
and CSB are low.
RDB
Input
Input
I/O
D2
C1
WRB
The active low write strobe (WRB) signal is low during a
S/UNI-2488 register write access. The D[15:0] bus contents
are clocked into the addressed register on the rising WRB
edge while CSB is low.
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
N1
The bi-directional data bus, D[15:0], is used during
S/UNI-2488 read and write accesses.
P4
N2
M1
M2
N4
L1
D[8]
D[7]
M3
L2
D[6]
D[5]
D[4]
D[3]
K1
M4
K2
J1
D[2]
D[1]
K3
J2
D[0]
H1
The test register select signal (TRS) selects between normal
and test mode register accesses. TRS is high during test
mode register accesses, and is low during normal mode
register accesses. TRS may be tied low.
A[13]/TRS
Input
D28
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
39
PMC [ PMC-SIERRA, INC ]
