PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
13.3 Packet Over SONET/SDH (POS) Level 3 System Interface
The Receive POS Level 3 System Interface Timing diagram (Figure 24) illustrates the operation
of the system side receive interface. The SUNI-2488 performs the polling operation internally,
selects the PHY for which data is to be transferred, and pushes data to the downstream reader.
When data is available, the RVAL signal is asserted. RSX is also asserted in cycle 2 to indicate
that the PHY address for which data is being transferred is present on RDAT[31:0]. At cycle 3,
RSOP is asserted to indicate that the RDAT[31:24] contains the first byte of a packet. RENB is
deasserted in cycle 4 because the downstream device wants to pause the data transfer.
Data transfer continues until cycle 10 when RVAL is deasserted. At cycle 12 and 13, the last two
transfers for the packet are performed. In cycle 13, REOP signals the last byte of the packet is
contained in RDAT[31:0] and the value of RMOD[1:0] indicates which bytes in RDAT[31:0] contain
valid data. RERR is asserted along with REOP if errors were detected in this packet (aborted,
length violation, FIFO overrun, FCS errors) so the downstream device may discard the packet. In
cycle 14, a new transfer is initiated by reasserting RSX and a new PHY address on RDAT[31:0].
The burst length of any transfer can be limited by setting the RXPHY’s BURST_SIZE[7:0] register
bits. The polling algorithm used for selecting the order in which data from different PHYs are
transferred is completely user programmable using the CALENDAR_LENGTH[6:0],
CALENDAR_ADDR[6:0] and CALENDAR_DATA[5:0] register bits of the RXPHY.
The FIFO threshold at which data transfer begins is set by the RXSDQ’s DT[7:0] register bits.
ATM cells can be transferred through the PL3 interface as fixed length packets. The DT[7:0]
value should be set so that only complete ATM cells are transferred.
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PMC [ PMC-SIERRA, INC ]
