PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
12.1.6 APS Parallel to Serial Converter (PISO)
The APISO is a parallel-to-serial converter designed for high-speed transmit operation, supporting
up to 777.6 Mb/s.
12.1.7 LVDS Transmitter (TXLV)
The TXLV is a 777.6 Mb/s Low Voltage Differential Signaling (LVDS) Transmitter according to the
IEEE 1596.3-1996 LVDS Specification. The TXLV accepts 777.6 Mbit/s differential data from the
APSIO circuit and transmits the data off-chip as a low voltage differential signal. The TXLV uses
the reference current and voltage from the TXLVREF to control the output differential voltage
amplitude and the output common-mode voltage.
12.2 SONET/SDH Frame Mappings and Overhead Byte Usage
12.2.1 ATM Mapping
The S/UNI-2488 processes the ATM cell mapping for STS-48c (STM-16c) as shown below in
Figure 18. The S/UNI-2488 processes the transport and path overhead required to support ATM
UNIs and NNIs. In addition, the S/UNI-2488 provides support for the APS bytes, the data
communication channels and provides full control and observability of the transport and path
overhead bytes through register access. In Figure 18, the STS-48c (STM-16c) mapping is shown.
In this mapping, fifteen stuff columns are included in the SPE. No other options are provided.
Figure 18 ATM Mapping
4320 Bytes
Transport
Overhea
d
4176 Bytes
Section
Overhea
d
J1
B3
C2
G1
F2
H4
Z3
Z4
Z5
ATM Cell
F
I
X
E
D
F
I
X
E
D
Pointer
9
ATM Cell
Bytes
Line
Overhea
d
S
T
U
F
F
S
T
U
F
F
ATM Cell
ATM Cell
12.2.2 Packet Over SONET Mapping
The S/UNI-2488 processes the Packet Over SONET mapping for STS-48c (STM-16c) as shown
below in Figure 19. The S/UNI-2488 processes the transport and path overhead required to
support Packet Over SONET applications. In addition, the S/UNI-2488 provides support for the
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
433
PMC [ PMC-SIERRA, INC ]
